Sampled amplitude read channel employing a remod/demod sequence detector guided by an error syndrome

ABSTRACT

A sampled amplitude read channel is disclosed for disk storage systems that employs a remod/demod sequence detector guided by an error syndrome of an error detection code (EDC). The remod/demod sequence detector comprises: a conventional trellis type maximum likelihood sequence detector, such as a Viterbi detector, for detecting a preliminary binary sequence from the channel sample values; a syndrome generator for generating an error syndrome in response to the preliminary binary sequence; a remodulator for remodulating the detected binary sequence into a sequence of estimated ideal sample values; a sample error generator for subtracting the channel samples from the estimated samples to generate a sample error sequence; an error pattern detector for detecting potential error events in the sample error sequence; and an error corrector for correcting the preliminary binary sequence when the error syndrome indicates that an error occurred. In the embodiment disclosed herein, the error syndrome is generated as the parity over a predetermined number of bits. When a parity error occurs, a correction is made corresponding to the most likely error event detected. Guiding the remod/demod sequence detector with an error syndrome avoids miscorrections that may otherwise occur in conventional remod/demod sequence detectors.

CROSS REFERENCE TO RELATED APPLICATIONS AND PATENTS

This application is related to other co-pending U.S. patentapplications, namely application Ser. No. 08/681,678 entitled "A SampledAmplitude Read Channel Employing Interpolated Timing Recovery and aRemod/Demod Sequence Detector," Ser. No. 08/681,692 entitled "A Rate16/17 ENDEC With Independent High/Low Byte Decoding," and Ser. No.08/640,351 entitled "Adaptive Equalization and Interpolated TimingRecovery in a Sampled Amplitude Read Channel for Magnetic Recording."This application is also related to several U.S. patents, namely U.S.Pat. No. 5,359,631 entitled "Timing Recovery Circuit for SynchronousWaveform Sampling," U.S. Pat. No. 5,291,499 entitled "Method andApparatus for Reduced-Complexity Viterbi-Type Sequence Detectors," U.S.Pat. No. 5,297,184 entitled "Gain Control Circuit for SynchronousWaveform Sampling," U.S. Pat. No. 5,329,554 entitled "Digital PulseDetector," U.S. Pat. No. 5,576,904 entitled "Timing Gradient SmoothingCircuit in a Synchronous Read Channel," U.S. Pat. No. 5,585,975 entitled"Equalization for Sample Value Estimation and Sequence Detection in aSampled Amplitude Read Channel," and U.S. Pat. No. 5,424,881 entitled"Synchronous Read Channel." All of the above-named patent applicationsand patents are assigned to the same entity, and all are incorporatedherein by reference.

FIELD OF INVENTION

The present invention relates to the control of storage systems fordigital computers (such as magnetic and optical disk drives),particularly to a sampled amplitude read channel that employs aremod/demod sequence detector guided by an error syndrome of an errordetection code (EDC).

BACKGROUND OF THE INVENTION

Computer storage systems (such as optical, magnetic, and the like)record digital data onto the surface of a storage medium, which istypically in the form of a rotating magnetic or optical disk, byaltering a surface characteristic of the disk. The digital data servesto modulate the operation of a write transducer (write head) whichrecords binary sequences onto the disk in radially concentric or spiraltracks. In magnetic recording systems, for example, the digital datamodulates the current in a write coil in order to record a series ofmagnetic flux transitions onto the surface of a magnetizable disk. Andin optical recording systems, for example, the digital data may modulatethe intensity of a laser beam in order to record a series of "pits" ontothe surface of an optical disk. When reading this recorded data, a readtransducer (read head), positioned in close proximity to the rotatingdisk, detects the alterations on the medium and generates a sequence ofcorresponding pulses in an analog read signal. These pulses are thendetected and decoded by read channel circuitry in order to reproduce thedigital sequence.

Detecting and decoding the pulses into a digital sequence can beperformed by a simple peak detector in a conventional analog readchannel or, as in more recent designs, by a discrete-time sequencedetector in a sampled amplitude read channel. Discrete-time sequencedetectors are preferred over simple analog pulse detectors because theycompensate for intersymbol interference (ISI) and are less susceptibleto channel noise. Consequently, discrete-time sequence detectorsincrease the capacity and reliability of the storage system. There areseveral well known discrete-time sequence detection methods includingdiscrete-time pulse detection (DPD), partial response (PR) with Viterbidetection, maximum likelihood sequence detection (MLSD),decision-feedback equalization (DFE), enhanced decision-feedbackequalization (EDFE), and fixed-delay tree-search with decision-feedback(FDTS/DF).

Unlike conventional peak detection systems, sampled amplitude recordingdetects digital data by interpreting, at discrete-time instances, theactual value of the pulse data. To this end, the read channel comprisesa sampling device for sampling the analog read signal, and a timingrecovery circuit for synchronizing the samples to the baud rate (codebit rate). Before sampling the pulses, a variable gain amplifier adjuststhe read signal's amplitude to a nominal value, and a low pass analogfilter filters the read signal to attenuate channel and aliasing noise.After sampling, a digital equalizer equalizes the sample valuesaccording to a desired partial response, and a discrete-time sequencedetector, such as a Viterbi detector, interprets the equalized samplevalues in context to determine a most likely sequence for the digitaldata (i.e., maximum likelihood sequence detection (MLSD)). MLSD takesinto account the effect of ISI and channel noise in the detectionalgorithm, thereby decreasing the probability of a detection error. Thisincreases the effective signal to noise ratio and, for a given (d,k)constraint, allows for significantly higher data density as compared toconventional analog peak detection read channels.

The application of sampled amplitude techniques to digital communicationchannels is well documented. See Y. Kabal and S. Pasupathy, "PartialResponse Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934,September 1975; and Edward A. Lee and David G. Messerschmitt, "DigitalCommunication", Kluwer Academic Publishers, Boston, 1990; and G. D.Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278,March 1973.

Applying sampled amplitude techniques to magnetic storage systems isalso well documented. See Roy D. Cideciyan, Francois Dolivo, WalterHirt, and Wolfgang Schott, "A PRML System for Digital MagneticRecording", IEEE Journal on Selected Areas in Communications, Vol. 10No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection ofClass IV Partial Response on a Magnetic Recording Channel", IEEE Trans.Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al,"Implementation of PRML in a Rigid Disk Drive", IEEE Trans. onMagnetics, Vol. 27, No. 6, November 1991; and Carley et al, "AdaptiveContinous-Time Equalization Followed By FDTS/DF Sequence Detection",Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3;and Moon et al, "Constrained-Complexity Equalizer Design for Fixed DelayTree Search with Decision Feedback", IEEE Trans. on Magnetics, Vol. 30,No. 5, September 1994; and Abbott et al, "Timing Recovery For AdaptiveDecision Feedback Equalization of The Magnetic Storage Channel",Globecom'90 IEEE Global Telecommunications Conference 1990, San Diego,Calif., November 1990, pp.1794-1799; and Abbott et al, "Performance ofDigital Magnetic Recording with Equalization and Offtrack Interference",IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffiet al, "Adaptive Equalization in Magnetic-Disk Storage Channels", IEEECommunication Magazine, February 1990; and Roger Wood, "EnhancedDecision Feedback Equalization", Intermag'90.

It is a general perception in the prior art that higher order readchannels provide an increase in performance because less equalization isrequired to match the read signal to the desired partial response, andbecause higher order read channels tend to perform better at higher datadensities. However, the trade-off in higher order read channels is theincrease in complexity. For example, a Partial Response Class-IV (PR4)read channel, which has a transfer function of 1-D², can be implementedsimply as a pair of two-state sliding threshold detectors (see the abovereferenced paper entitled "A PRML System for Digital MagneticRecording"), but it exhibits a loss in performance due to the amount ofequalization required to match the read signal to the PR4 response. AnExtended Partial Response Class-IV (EPR4) read channel, which has atransfer function of (1-D)(1+D)², requires less equalization whichresults in performance gain over the PR4 read channel. However, a fullEPR4 detector requires a significantly more complex add-compare-select(ACS) state machine that operates according to an eight-state trellis.

A recent development in sampled amplitude read channels reaches acompromise between the opposing design criteria of performance versuscomplexity. This new technique, referred to as remod/demod sequencedetection, typically employs: a conventional trellis type maximumlikelihood sequence detector, such as a Viterbi detector, for detectinga preliminary binary sequence from the channel sample values; aremodulator for remodulating the detected binary sequence into asequence of estimated ideal sample values; a sample error generator forsubtracting the channel samples from the estimated samples to generate asample error sequence; an error pattern detector for detecting potentialerror events in the sample error sequence; and an error corrector forcorrecting the preliminary binary sequence when an error event exceeds apredetermined threshold. Examples of a remod/demod sequence detector aredisclosed in the above referenced co-pending U.S. patent applicationentitled "A Sampled Amplitude Read Channel Employing Interpolated TimingRecovery and a Remod/Demod Sequence Detector," and in a paper by RogerWood entitled "Turbo-PRML: A Compromise EPRML Detector," IEEETransaction on Magnetics, Vol. 29, No. 6, pp. 4018, November 1993.

The error pattern detector in a remod/demod sequence detector istypically implemented as a number of finite-impulse-response (FIR)filters matched to the dominant error events of the Viterbi sequencedetector. In this manner, when the Viterbi sequence detector makes anerror, the probability is high that the error pattern detector will"catch" the error so it can be corrected. A general perception in theprior art is that the error pattern detector should detect the errorevents in a partial response domain higher in order than the Viterbisequence detector, which is consistent with the general perception thathigher order read channels outperform lower order read channels asdescribed above. For example, in the two aforementioned remod/demodsequence detectors, the Viterbi sequence detector operates in the PR4domain, while the error pattern detector searches for error events inthe EPR4 domain. This particular implementation approaches theperformance gain provided by a full eight-state EPR4 Viterbi sequencedetector, but with a significant reduction in hardware. The PR4 Viterbidetector can be implemented as a pair of sliding threshold detectors,and the error pattern detector as a bank of FIR filters.

Although the prior art PR4 remod/demod sequence detectors provide aperformance gain that approaches that of EPR4 with a significantreduction in hardware, the prior art does not suggest the optimumimplementation for an EPR4 remod/demod sequence detector. At best, theprior art would suggest to detect the preliminary binary sequence in theEPR4 domain, and to detect the error events in the EEPR4 domain (whichhas the transfer function (1-D)(1+D)³). Another drawback of prior artremod/demod sequence detectors is the potential to make miscorrectionswhen an error is falsely detected, or when the location of an error ismisdetected. For example, the aforementioned remod/demod sequencedetector disclosed by Roger Wood can misdetect an error because itdetects the first error event to exceed a predetermined threshold,rather than detecting when the maximum error event occurs. Theabove-referenced co-pending patent application overcomes this drawbackby detecting peaks in the error events; however, a miscorrection canstill occur if the error event points to a non-error.

There is, therefore, a need for a remod/demod sequence detector in asampled amplitude read channel for disk storage systems that provides aperformance gain over a conventional EPR4 sequence detector. Anotherobject of the present invention is to modify conventional remod/demodsequence detectors, including the aforementioned prior art PR4remod/demod sequence detectors, to reduce the probability ofmiscorrections.

SUMMARY OF THE INVENTION

A sampled amplitude read channel is disclosed for disk storage systemsthat employs a remod/demod sequence detector guided by an error syndromeof an error detection code (EDC). The remod/demod sequence detectorcomprises: a conventional trellis type maximum likelihood sequencedetector, such as a Viterbi detector, for detecting a preliminary binarysequence from the channel sample values; a syndrome generator forgenerating an error syndrome in response to the preliminary binarysequence; a remodulator for remodulating the detected binary sequenceinto a sequence of estimated ideal sample values; a sample errorgenerator for subtracting the channel samples from the estimated samplesto generate a sample error sequence; an error pattern detector fordetecting potential error events in the sample error sequence; and anerror corrector for correcting the preliminary binary sequence when theerror syndrome indicates that an error occurred. In the embodimentdisclosed herein, the error syndrome is generated as the parity over apredetermined number of bits. When a parity error occurs, a correctionis made corresponding to the most likely error event detected. Guidingthe remod/demod sequence detector with an error syndrome avoidsmiscorrections that may otherwise occur in conventional remod/demodsequence detectors.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and advantages of the present invention willbe better understood by reading the following detailed description ofthe invention in conjunction with the drawings, wherein:

FIG. 1A shows a magnetic disk storage medium comprising a plurality ofconcentric data tracks and embedded servo wedges, where the data tracksare partitioned into a plurality of data sectors.

FIG. 1B shows an example format of a data sector comprising a preamblefor frequency/phase locking timing recovery, a sync mark for symbolsynchronizing the user data, and redundancy symbols of an errorcorrection code (ECC).

FIG. 2 is a block diagram of a sampled amplitude read channel comprisingthe remod/demod sequence detector of the present invention.

FIG. 3A is a state transition diagram of a conventional Partial Responseclass-IV (PR4) Viterbi sequence detector.

FIG. 3B is a PR4 trellis diagram corresponding to the PR4 statetransition diagram of FIG. 3A.

FIGS. 4A, 4B and 4C show the dominant error events that can occur in asampled amplitude read channel in NRZ, PR4 and EPR4 space, respectively.

FIG. 5 is a detailed block diagram of the remod/demod sequence detectorof FIG. 2 showing one aspect of the present invention: a syndromegenerator for detecting when an error occurs in the preliminary binarysequence output by the Viterbi sequence detector.

FIG. 6 is a detailed block diagram of the remod/demod sequence detectorshowing another aspect of the present invention: PR4 equalized channelsamples, an EPR4 Viterbi sequence detector, and a PR4/EPR4 error patterndetector.

FIG. 7 shows the state transition diagram of the EPR4 Viterbi sequencedetector of FIG. 6.

FIG. 8 is a more detailed block diagram of the remodulator of thepresent invention.

FIG. 9 is a block diagram of the error pattern detector in theremod/demod sequence detector of the present invention.

FIG. 10 is a flow chart that illustrates the operation of the syndromegeneration (parity) and error correction process according to one aspectof the present invention.

FIGS. 11A and 11B illustrate the syndrome generation (parity) when anerror event occurs across code word boundaries.

FIG. 12 is a block diagram of the error corrector in the remod/demodsequence detector of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Data Format

FIG. 1A shows a conventional data format of a magnetic disk storagemedium comprising a series of concentric, radially spaced data tracks14, wherein each data track 14 comprises a plurality of sectors 16 withembedded servo wedges 18. A servo controller (not shown) processes theservo data in the servo wedges 18 and, in response thereto, positions aread/write head over a selected track. Additionally, the servocontroller processes servo bursts within the servo wedges 18 to keep thehead aligned over a centerline of the selected track while writing andreading data. The servo wedges 18 may be detected by a simplediscrete-time pulse detector or by the discrete-time sequence detectorof FIG. 2. The format of the servo wedges 18 includes a preamble and async mark, similar to the user data sectors 16 described below withreference to FIG. 1B.

Zoned recording is a technique known in the art for increasing thestorage density by recording the user data at different rates inpredefined zones between the inner diameter and outer diameter tracks.The data rate can be increased at the outer diameter tracks due to theincrease in circumferential recording area and the decrease inintersymbol interference. This allows more data to be stored in theouter diameter tracks as is illustrated in FIG. 1A where the disk ispartitioned into an outer zone 20 comprising fourteen data sectors pertrack, and an inner zone 22 comprising seven data sectors per track. Inpractice, the disk may actually be partitioned into several zones atvarying data rates.

FIG. 1B shows the format of a conventional data sector 16 comprised ofan acquisition preamble 24, a sync mark 26, and a data field 28including appended ECC bytes 30 for use in detecting and correctingerrors in the user data upon readback. Timing recovery 68 of FIG. 2processes the acquisition preamble 24 to acquire the correct datafrequency and phase before reading the user data field 28, and the syncmark 26 demarks the beginning of the user data field 28 for use insymbol synchronizing the user data.

Sampled Amplitude Read Channel

Referring now to FIG. 2, shown is a block diagram of the sampledamplitude read channel of the present invention. During a writeoperation, the read channel receives user data over line 32 from thehost system. A data generator 34 generates the preamble 24 of FIG. 1B(for example 2T preamble data) written to the disk prior to writing theuser data 28. The data generator 34 also generates a sync mark 26 foruse in symbol synchronizing to the user data during a read operation. A16/17 RLL encoder 36 encodes the user data according to a run-lengthlimited RLL (d,k) constraint to generate an encoded binary sequence b(n)38. The preferred embodiment for the 16/17 RLL encoder 16 is disclosedin the above referenced co-pending U.S. patent application "A Rate 16/17ENDEC With Independent High/Low Byte Decoding." A precoder 40 precodesthe binary sequence b(n) 38 in order to compensate for the transferfunction of the recording channel 42 and equalizing filters. A paritygenerator 44 computes the parity over a section or block of bits outputby the precoder 40 and appends a parity bit to each block to form EDCcode words. The sequence of bits ˜b(n) 46 in the EDC code words areconverted into symbols a(n) 50 by translating 48 ˜b(N)=0 into a(N)=-1,and ˜b(N)=1 into a(N)=+1 (the symbols ˜b(n) 46 are referred to as NRZdata). Write circuitry 52, responsive to the symbols a(n) 50, modulatesthe current in the recording head coil (or intensity of a laser beam) atthe zone baud rate to record a sequence of transitions onto the disk 42,wherein the transitions represent the recorded data. A frequencysynthesizer 54 provides a baud rate write clock 56 to the writecircuitry 52 and is adjusted by a baud or channel data rate signal (CDR)58 according to the current zone the recording head is over.

When reading the recorded binary sequence from the media, timingrecovery 68 first locks to the write frequency by selecting, as theinput to the read channel, the write clock 56 through a multiplexer 70.Once locked to the write frequency, the multiplexer 70 selects thesignal 72 from the read head as the input to the read channel in orderto acquire the acquisition preamble 24 recorded on the disc prior to therecorded user data 28 as shown in FIG. 1B. A variable gain amplifier 62adjusts the amplitude of the analog read signal 60, and an analogreceive filter 62 provides initial equalization toward the desiredresponse as well as attenuating aliasing noise. A sampling device 64samples the analog read signal 66 from the analog filter 62, and adiscrete-time equalizer filter 74 provides further equalization of thesample values 76 toward the desired response. In partial responserecording, for example, the desired partial response is often selectedfrom Table 1:

                  TABLE 1    ______________________________________    Channel   Transfer Function                            Dipulse Response    ______________________________________    PR4       (1 - D) (1 + D)                            0, 1, 0, -1, 0, 0, 0, . . .    EPR4      (1 - D) (1 + D).sup.2                            0, 1, 1, -1, -1, 0, 0, . . .    EEPR4     (1 - D) (1 + D).sup.3                            0, 1, 2, 0, -2, -1, 0, . . .    ______________________________________

The discrete equalizer filter 74 may be implemented as a real-timeadaptive filter which compensates for parameter variations over the discradius (i.e., zones), disc angle, and environmental conditions such astemperature drift.

After equalization, the equalized sample values 78 are applied to adecision directed gain control 80 and timing recovery 68 circuit foradjusting the amplitude of the read signal 60 and the frequency andphase of the sampling device 64, respectively. Gain control 80 adjuststhe gain of variable gain amplifier 62 over line 82 in order to matchthe magnitude of the channel's frequency response to the desired partialresponse, and timing recovery 68 adjusts the frequency of samplingdevice 64 over line 84 in order to synchronize the equalized samples 78to the baud rate. Frequency synthesizer 54 provides a course centerfrequency setting to the timing recovery circuit 68 over line 86 inorder to center the timing recovery frequency over temperature, voltage,and process variations.

In the preferred embodiment, the discrete-time equalizer 74 equalizesthe 76 sample values into a PR4 response so that a simple slicer circuit(not shown) can generate estimated sample values for use in timingrecovery 68 and gain control 80. A slicer generates estimated samplevalues simply by comparing the channel samples to programmable positiveand negative thresholds according to Table 2:

                  TABLE 2    ______________________________________    Sample Value   Slicer Output    ______________________________________    y >= T1        +1    -T2 <= y < T1   0    y < -T2        -1    ______________________________________

In Table 2, y is the sample value and T1 and -T2 are the positive andnegative thresholds, respectively. If the discrete-time equalizer 74 isreal time adaptive, then the estimated sample values generated by theslicer are also input into the equalizer 74 over line 98 for use in theadaptive equalization algorithm. For implementation details concerningsample value estimation for timing recovery 68 and gain control 80, seethe above referenced U.S. Pat. No. 5,585,975, "Equalization for SampleValue Estimation and Sequence Detection in a Sampled Amplitude ReadChannel." For details on the preferred embodiment for an adaptivediscrete-time equalizer, see the above referenced co-pending U.S. patentapplication, "Adaptive Equalization and Interpolated Timing Recovery ina Sampled Amplitude Read Channel for Magnetic Recording." Theaforementioned co-pending U.S. patent application also illustrates analternative embodiment for synchronous-sampling timing recovery 68:sampling the analog read signal asynchronously and interpolating theasynchronous samples to generate the synchronous samples.

The synchronous, equalized samples 78 are ultimately input into aremod/demod sequence detector 88 which detects an estimated binarysequence b(n) 90 from the sample values. An RLL decoder 92 decodes theestimated binary sequence b(n) 90 from the sequence detector 88 intoestimated user data 94. A data sync detector 96 detects the sync mark 26(shown in FIG. 1B) in the data sector 16 in order to frame operation ofthe RLL decoder 92. In the absence of errors, the estimated binarysequence b(n) 90 matches the recorded binary sequence b(n) 38, and thedecoded user data 94 matches the recorded user data 32. A detaileddescription of the remod/demod sequence detector 88 is provided in thefollowing section.

Trellis Sequence Detector

The sampled amplitude read channel of the present invention employspartial response (PR) equalization and maximum likelihood (ML) sequencedetection (e.g., Viterbi sequence detection). To understand the sequencedetection operation, consider the trellis sequence detector for apartial response class-IV (PR4) read channel. The transfer function forthis channel is represented by the polynomial (1-D²) where D is a delayoperator referring to the channel or baud rate. With the input symbolsa(n) taking on the values +1 or -1, the output channel samples take onvalues in the set {+2,0,-2}. A trellis sequence detector, such as aViterbi detector for PR4, operates by examining the channel samples incontext to determine a most likely estimated data sequence associatedwith the samples.

Operation of the PR4 sequence detector is understood from its statetransition diagram shown in FIG. 3A. Each state 100 is represented bythe last two input symbols a(n) 102 (after preceding), and each branchfrom one state to another is labeled with the current input symbol a(n)102 and the corresponding sample value 104 it will produce duringreadback. Thus, during readback the sample sequence can be demodulatedinto the input symbol sequence a(n) (recorded sequence) according to thestate transition diagram. However, noise in the read signal due totiming errors, miss-equalization, etc., will obfuscate the readbacksample values and introduce ambiguity in the correct demodulated datasequence. The function of the sequence detector, then, is to resolvethis ambiguity by demodulating the sample values into a most likely datasequence.

The demodulation process of the sequence detector is understood byrepresenting the state transition diagram of FIG. 3A as a trellisdiagram shown in FIG. 3B. The trellis diagram represents a time sequenceof sample values and the possible recorded input sequences a(n) thatcould have produced the sample sequence. For each possible inputsequence a(n), an error metric is computed relative to a differencebetween the sequence of expected sample values that would have beengenerated in a noiseless system and the actual sample values read fromthe channel. For instance, a Euclidean metric is computed as theaccumulated square difference between the expected and actual samplevalues. The input sequence a(n) that generates the smallest Euclideanmetric is the most likely sequence to have created the actual samplevalues; this sequence is therefore selected as the output of thesequence detector.

To facilitate the demodulation process, the sequence detector comprisespath memories for storing each of the possible input sequences a(n) anda corresponding metric. A well known property of the sequence detectoris that the paths storing the possible input sequences will "merge "into a most likely input sequence after a certain number of samplevalues are processed (as long as the input sequence is appropriatelyconstrained). In fact, the maximum number of path memories needed equalsthe number of states in the trellis diagram; the most likely inputsequence will always be represented by one of these paths, and thesepaths will eventually merge into one path (i.e., the most likely inputsequence) after a certain number of sample values are processed.

The "merging" of path memories is understood from the trellis diagram ofFIG. 3B where the "survivor" sequences are represented as solid lines.Notice that each state in the trellis diagram can be reached from one oftwo states; that is, there are two transition branches leading to eachstate. With each new sample value, the Viterbi algorithm recursivelycomputes a new error metric and retains a single survivor sequence foreach state corresponding to the minimum error metric. In other words,the Viterbi algorithm will select one of the two input branches intoeach state since only one of the branches will correspond to the minimumerror metric. As a result, the paths through the trellis correspondingto the branches not selected will merge into the paths that wereselected. Eventually, all of the survivor sequences will merge into onepath through the trellis which represents the most likely estimated datasequence to have generated the sample values as shown in FIG. 3B.

Although trellis sequence detection is "maximum likelihood" (or anapproximation thereof depending on how the equalizers color the noise),the sequence detector can still make an error in detecting the outputsequence if enough destructive noise is present in the read signal.FIGS. 4A-4C illustrate the sample error sequences associated with thedominant minimum distance error events in NRZ, PR4 and EPR4 domains,respectfully. In general, a higher order sequence detector willoutperform a lower order sequence detector due to the number of samplesthe error event affects. Consider, for example, the first error event inthe NRZ domain shown in FIG. 4A. This error event corrupts two samples(two output bits) in the PR4 domain of FIG. 4B and four samples in theEPR4 domain of FIG. 4C. Thus, "spreading out" the error event reducesthe probability of a detection error. From this observation, it has beendetermined that the sample errors can be evaluated in a higher orderdomain to determine when a lower order sequence detector will make anerror. This is the essential function of a conventional remod/demodsequence detector: detect a preliminary binary sequence with a lowerorder trellis sequence detector (e.g., with PR4 Viterbi detector), andevaluate the sample errors in a higher order domain (e.g., in EPR4domain) to determine when the PR4 Viterbi detector has most likely madean error.

The generalization that the sample errors will provide more informationif evaluated in a higher order domain, however, is only true for certainerror events depending on the channel density employed. As discussed inmore detail below, the applicant's have discovered that for certainerror events and at certain user densities, it is better to evaluate thesample errors in a lower order domain (e.g., PR4 as opposed to EPR4).Another drawback of conventional remod/demod sequence detectors is thepotential of miscorrections. That is, a conventional remod/demodsequence detector can determine only when the primary Viterbi sequencedetector has probably made an error without a means for verifying thatan error actually occurred. The present invention provides a performanceenhancement by reducing the likelihood of a miscorrection through theuse of an error detection code (EDC). This aspect of the presentinvention is discussed in the following section.

Syndrome Guided Remod/Demod Sequence Detector

FIG. 5 shows a block diagram of the remod/demod sequence detector 88 ofFIG. 2 guided by a syndrome generator 110 according to one aspect of thepresent invention. Guiding the detector using an error syndrome isapplicable to a conventional remod/demod sequence detector, such as theaforementioned PR4 remod/demod sequence detectors, or it can be appliedto the EPR4 remod/demod sequence detector described in the next section.The general operation of a remod/demod sequence detector is as follows.

The equalized samples 78 output by the discrete equalizer 74 of FIG. 2are processed by a conventional trellis sequence detector 112, such as aViterbi sequence detector, to detect a preliminary binary sequence 114.A remodulator 116 remodulates the preliminary binary sequence 114 intoan estimated sequence of ideal sample values 117 which are subtractedfrom the channel samples 78 (after passing through a delay 118 toaccount for the delay in the trellis detector 112) to generate asequence of sample error values 120. An error pattern detector 122processes the sequence of sample errors 120 to detect when the trellisdetector 112 most likely made an error. The error pattern detector 122typically comprises a plurality of finite-impulse-response (FIR) filtersmatched to the dominant error events of the trellis detector 112 (e.g.,FIG. 4). In prior remod/demod sequence detectors, an error in thepreliminary binary sequence 114 is corrected by an error corrector 124when the output of an FIR filter matched to a particular error eventexceeds a predetermined threshold and the detected binary sequence 114is consistent with the detected error event. However, the preliminarybinary sequence can be miscorrected if the error event actually pointsto a non-error in the detected binary sequence.

To decrease the probability of miscorrections, the present inventionemploys an error detection code (EDC) capable of detecting when an erroroccurs in a predetermined number of bits (i.e., a block) of the detectedbinary sequence. In the preferred embodiment, the EDC is simplygenerated as the parity over four of the 17-bit code words generated bythe 16/17 RLL encoder 36 of FIG. 2 after precoding 40 (i.e., parity overthe bits in the NRZ domain). The parity bit output by the paritygenerator 44 is then appended to the four 17-bit code words to create a69-bit EDC code word written to the disk 42. Upon read back, thesyndrome generator 110 of FIG. 5 processes the detected binary sequenceoutput by the trellis sequence detector 112 to generate an errorsyndrome 126 (e.g., parity) which indicates whether an error occurred inthe EDC code word (i.e., the 69-bit EDC code word).

When the error syndrome 126 indicates that the EDC code word contains anerror, the error corrector 124 corrects the preliminary binary sequence114 using the error event detected by the error pattern detector 122most likely to have caused the error (e.g., the maximum error event). Inthis manner, the probability of a miscorrection decreases because theerror syndrome of the EDC only allows a correction to occur when anerror is present. A miscorrection can still occur if the selected errorevent used to make the correction is the wrong errorevent--nevertheless, it is still an improvement over the prior art.

An error that occurs in a current EDC code word may propagate over thecode word boundaries to the previous or following EDC code words.Circuitry is provided in the error pattern detector 122 to account forthis possibility--an example embodiment for this circuitry is discussedin greater detail below with reference to FIGS. 9, 10, 11A, and 11B, andwith reference to FIG. 6 which shows the preferred embodiment for theEPR4 remod/demod sequence detector of the present invention.

Those skilled in the art will appreciate that the present inventioncould be modified to operate with an error detection code other thanparity. Furthermore, the syndrome guiding aspect of the presentinvention is applicable to the aforementioned conventional remod/demodsequence detectors, as well as to more advanced detectors such as theEPR4 remod/demod detector described in the following section.

EPR4 Remod/Demod Sequence Detector

In another aspect of the present invention, a conventional EPR4 sequencedetector is enhanced by applying the remod/demod technique in a mannernot suggested by the prior art. The preferred embodiment for thissequence detector is shown in FIG. 6. As discussed above with referenceto FIG. 2, the channel samples 78 are equalized into a PR4 response sothat a simple slicer circuit can generate the estimated sample valuesfor use by timing recovery 68, gain control 80, and the adaptiveequalizer 74. The PR4 samples 78 are converted to EPR4 samples 132 by asimple 1+D filter 130 shown in FIG. 6. An EPR4 sequence detector 134detects a preliminary NRZ sequence 136 from the EPR4 samples, and theNRZ sequence is then remodulated by remodulator 138 to generate asequence of estimated sample values 140 similar to FIG. 5. The estimatedsample values 140 are subtracted from the PR4 channel samples (afterpassing through a delay 142 to account for the delay in the EPR4detector 134) to generate a sequence of sample error values 144. APR4/EPR4 error pattern detector 146 processes the sample error values144 and saves the correction value and location of the most likely errorevent. A syndrome generator 148 generates an error syndrome (e.g.,parity) over a block of the NRZ sequence 136 and, if the error syndromeindicates that the EPR4 detector 134 made a detection error, a signedNRZI sequence 154 (generated by the remodulator 138) is corrected by anerror corrector 150 using the most likely error event generated by theerror pattern detector 146.

The EPR4 sequence detector 134 of FIG. 6 operates according to the statetransition diagram shown in FIG. 7, which is similar to the statetransition diagram of FIG. 3A described above with reference to a PR4read channel. The transfer function of an EPR4 read channel is:

    1+D-D.sup.2 -D.sup.3.

The channel output is defined as the convolution of the input symbolsa(n) 50 of FIG. 2 with the dipulse response of the above EPR4 transferfunction (+1, +1, -1, -1). Therefore, the current output of the EPR4read channel is determined from the current and three previous inputsymbols a(n). Each state in the state transition diagram of FIG. 7represents one of eight possible values for the three previous inputsymbols a(n), and each transition branch is labeled with an x/y where xis the current input symbol a(n) and y is the corresponding channeloutput it will generate in the NRZ domain. The channel output yrepresents the output detected by the EPR4 sequence detector; it is inthe NRZ domain because the parity bit is generated in the NRZ domain(i.e., by the parity generator 44 of FIG. 2).

The remodulator 138 of FIG. 6 comprises a 1-D filter 152 for convertingthe NRZ sequence 136 into a signed NRZI (SNRZI) sequence 154, a partialerasure compensator 156 which adjusts the magnitude of the SNRZIsequence 154 to account for the effect of partial erasure, and a 1+Dfilter 158 for converting the output of the partial erasure compensator156 into a sequence of estimated PR4 sample values 140. A more detailedblock diagram of the remodulator 138 of FIG. 6 is shown in FIG. 8.

The partial erasure compensator 156 adjusts the magnitude of the SNRZIsamples to account for the non-linear reduction in pulse amplitudecaused by adjacent flux transitions. That is, the magnitude of the SNRZIsample at S_(n-1) 160 is reduced by A_(PE) 162 (where A_(PE) <1) ifthere is an adjacent transition either at S_(n) 164 or at S_(n-2) 166,and the magnitude of S_(n-1) 160 is reduced by (A_(PE) +A_(PE)) if thereis an adjacent transition both at S_(n) 164 and at S_(n-2) 166. Toimplement the partial erasure compensator 156, the SNRZI samples,designated S_(n), S_(n-1) and S_(n-2), index a lookup table 168 whichoutputs a modified value for S_(n-1) (designated SP_(n-1) 170) inaccordance with the entries shown in Table 3.

                  TABLE 3    ______________________________________                MODIFIED              MODIFIED    SNRZI       SNRZI     SNRZI       SNRZI    S.sub.n-2           S.sub.n-1                  S.sub.n                        SP.sub.n-1                                S.sub.n-2                                     S.sub.n-1                                          S.sub.n                                              SP.sub.n-1    ______________________________________     0     +1      0    +1       0   -1    0  -1    -1     +1      0    +1 - A.sub.PE                                +1   -1    0  -1 + A.sub.PE     0     +1     -1    +1 - A.sub.PE                                 0   -1   +1  -1 + A.sub.PE    -1     +1     -1    +1 - (A.sub.PE  +                                +1   -1   +1  -1 + (A.sub.PE  +                        A.sub.PE)             A.sub.PE)    ______________________________________

After compensating for the effect of partial erasure, the modified SNRZIsamples SP_(n-1) 170 pass through a 1+D filter 158, thereby convertingthe SNRZI samples into an estimated PR4 sample sequence 140. Because thegain control 80 of FIG. 2 attempts to compensate for the non-lineareffect of partial erasure by adjusting the read signal amplitude towardan ideal PR4 magnitude on average, a gain multiplier 172 adjusts themagnitude of the remodulated PR4 sequence 140 to compensate for thisadjustment. The estimated PR4 sample sequence 174 at the output of thegain multiplier 172 is then subtracted from the actual read signalsample values 176 at adder 178 to generate a PR4 sample error sequence144.

The sample error sequence 144 is then processed by the PR4/ERP4 errorpattern detector 146 of FIG. 6, a more detailed diagram of which isprovided in FIG. 9. Through computer simulations it was determined that,for user densities of 1.8 to 2.5, the most dominant error event (thefirst error event shown in FIG. 4A) is best detected in the EPR4 domain,while the next most dominant error event (the second error event shownin FIG. 4A) is best detected in the PR4 domain. Therefore, the PR4/EPR4error pattern detector 146 of the present invention comprises two FIRfilters 180 of the form:

    (1+2D+D.sup.2)(1-D.sup.2) and 1-D+D.sup.3 -D.sup.4.

The first FIR filter is matched to the SNRZI (+1, -1) minimum distanceerror event in the EPR4 domain, and the second FIR filter is matched tothe SNRZI (+1, -2, +2, -1) minimum distance error event in the PR4domain.

To allow for further flexibility, a multiplexer 185 is provided toselectively configure the second error FIR error filter to detect theerror event in the EPR4 domain rather than in the PR4 domain. That is,the multiplexer 185 can select the intermediate output 187 from thefirst FIR filter in order to configure the second FIR filter into theform:

    (1+2D+D.sup.2)(1-D+D.sup.3 -D.sup.4)

which is matched to the SNRZI (+1, -2, +2, -1) minimum distance errorevent in the EPR4 domain. Detecting both error events in the EPR4 domainmay be desirable depending on the system dynamics and/or the recordingdensity employed.

For each error sample input into the error pattern detector, acomparator 182 selects the FIR filter with the largest absolutemagnitude output that corresponds to a valid error sequence as describedbelow. The output of the comparator 182 is then compared to a "currentmaximum" at comparator 184 and to a next maximum at comparator 186. The"current maximum" saves the maximum FIR output for the current EDC codeword being processed, and the "next maximum" saves the maximum FIRoutput for the following EDC code word.

The SNRZI sequence 154 generated by the remodulator 138 is buffered in aFIFO buffer 188 and compared to expected error sequences stored in alookup table 190. As each new sample value is processed, the output ofthe error filters 180 index the lookup table 190 over line 192 todetermine whether the detected SNRZI sequence 154 matches a valid errorsequence. The comparator 182 will only compare the output of the errorfilters 180 with corresponding valid error sequences (the output oferror filters corresponding to invalid error sequences are set to zero).When a potential error event is detected because the maximum valid FIRoutput 180 exceeds the current maximum or the next maximum at comparator184 or 186, the lookup table 190 outputs a correction sequencecorresponding to the detected error for the current and/or next EDC codeword, and the correction sequences are saved in registers 194 and 196,respectively.

The lookup table 190 of FIG. 9 operates according to Table 4 and Table 5below which show the expected SNRZI sequences resulting from the twodetected error events, E1 and E2, and the corresponding corrected outputsequences.

                  TABLE 4    ______________________________________    SNRZI Error (+1, -1)    Expected     Corrected         Expected                                          Corrected    SNRZI        SNRZI             SNRZI  SNRZI    E1      S.sub.n                  S.sub.n-1                         S.sub.n                             S.sub.n-1                                  E1     S.sub.n                                             S.sub.n-1                                                  S.sub.n                                                      S.sub.n-1    ______________________________________    E1 < 0  +1    -1     +0  +0   E1 > 0 -1  +1   -0  -0    E1 < 0  -0    -1     -1  +0   E1 > 0 +0  +1   +1  -0    E1 < 0  +1    -0     +0  +1   E1 > 0 -1  +0   -0  -1    E1 < 0  -0    -0     -1  +1   E1 > 0 +0  +0   +1  -1    ______________________________________

                  TABLE 5    ______________________________________    SNRZI Error (+1, -2, +2, -1)                      Corrected    Expected SNRZI      SNRZI    E2      S.sub.n                   S.sub.n-1                          S.sub.n-2                               S.sub.n-3                                    S.sub.n                                         S.sub.n-1                                              S.sub.n-2                                                   S.sub.n-3    ______________________________________    E2 < 0  -0     -1     +1   -0   -1   +1   -1   +1    E2 < 0  -0     -1     +1   -1   -1   +1   -1   +0    E2 < 0  +1     -1     +1   -0   +0   +1   -1   +1    E2 < 0  +1     -1     +1   -1   +0   +1   -1   +0    E2 > 0  +0     +1     -1   +0   +1   -1   +1   -1    E2 > 0  +0     +1     -1   +1   +1   -1   +1   -0    E2 > 0  -1     +1     -1   +0   -0   -1   +1   -1    E2 > 0  -1     +1     -1   +1   -0   -1   +1   -0    ______________________________________

The error events E1 and E2 can be positive or negative depending on thepolarity of the sample error sequence 144. The detected SNRZI sequencestored in the FIFO buffer 188 of FIG. 9 are compared to the "ExpectedSNRZI" sequences in the above lookup tables to determine whether a validcorrection can be made.

The outputs of comparators 184 and 186 enable operation of the lookuptable 190 as well as indicate the location of the error event in theSNRZI sequence 154 for the current and next EDC code words. The locationof the errors are stored in registers 198 and 200, respectively. Whenthe parity syndrome generated by the parity generator 148 of FIG. 6indicates a detection error in the current EDC code word, the errorcorrector 150 corrects the SNRZI sequence 154 using the correctedsequence stored in register 194 and the corresponding location of theerror stored in register 198.

The reason for storing the maximum FIR output and correspondingcorrection sequence and error location for the next EDC code word isbecause an error in the current EDC code word can propagate over thecode word boundaries to the previous or next EDC code word. Therefore,the error pattern detector 146 searches for error events starting withthe last two bits of the previous EDC code word and extending throughthe first three bits of the next EDC code word. This aspect of thepresent invention is better understood with reference to FIG. 10 whichis a flow diagram executed when processing a data sector, and FIG. 11Aand 11B which illustrate both the parity generation and maximum errorevent detection, including the case where an error extends over the EDCcode word boundaries.

FIG. 11A shows 74 bits of a current sector buffered in a FIFO buffer202, including the last two bits of a previous EDC code word, 69 bits ofa current EDC code word, and the first three bits of the next EDC codeword. The data stored in the FIFO buffer 202 is processed according tothe flow diagram of FIG. 10, wherein at step 204 the current parityCUR₋₋ PARITY, next parity NEXT₋₋ PARITY, current maximum FIR outputCUR₋₋ MAX, and next maximum FIR output NEXT₋₋ MAX are initialized tozero. A COUNTER is initialized to 3 to start with the first bit of thefirst EDC code word of the sector as shown in FIG. 11A.

At step 206, a branch is executed depending on the current COUNTER valuewhich represents a pointer into the FIFO buffer 202. If the COUNTERvalue is 3 through 71 at step 206, then the remod/demod detector isprocessing the data bits of a current EDC code word. At step 208, thecurrent parity CUR₋₋ PARITY is updated with the current NRZ bit 136output by the EPR4 sequence detector 134, and at step 210, the currentsample error value 144 is filtered by the FIR filters 180 in the errorpattern detector 146 of FIG. 9. The FIR filter with the maximum outputMAX₋₋ FIR that corresponds to a valid correction sequence from Table 4or Table 5 is selected at step 212, and the selected FIR filter isassigned to CUR₋₋ FIR. If the maximum FIR filter output MAX₋₋ FIR isgreater than the current maximum CUR₋₋ MAX at step 214, then at step 216the lookup table 190 of FIG. 9 compares the detected SNRZI sequencestored in FIFO buffer 188 to the expected SNRZI sequences thatcorrespond to the detected error event as shown in Table 4 and Table 5.If there is a match at step 216 indicating that a valid correction canbe made, then at step 218 the current maximum CUR₋₋ MAX is updated toMAX₋₋ FIR, the corresponding location of the detected error LOC CUR₋₋FIR! is assigned to CUR₋₋ LOC, and the corresponding correction sequencefrom Table 4 or Table 5 is assigned to CUR₋₋ COR. If the maximum FIRoutput MAX₋₋ FIR is not greater than the current maximum CUR₋₋ MAX atstep 214, or if a valid correction cannot be made at step 216, then step218 is skipped.

Another branch is executed at step 220 based on the current value of theCOUNTER. If the COUNTER value is 70 through 74, then the error patterndetector 146 begins searching for the maximum error event in the nextEDC code word. At step 222, the maximum FIR output is compared to NEXT₋₋MAX, the maximum value saved for the next EDC code word. If greater,then again the lookup table 190 of FIG. 9 compares the detected SNRZIsequence stored in FIFO buffer 188 to the expected SNRZI sequencesstored in Table 4 or Table 5. If there is a match at step 224 indicatingthat a valid correction can be made, then at step 226 the maximum FIRoutput for the next EDC code word NEXT₋₋ MAX is updated to MAX₋₋ FIR,the corresponding location of the detected error LOC CUR₋₋ FIR! isassigned to NEXT₋₋ LOC, and the corresponding correction sequence fromTable 4 or Table 5 is assigned to NEXT₋₋ COR. If the maximum FIR outputMAX₋₋ FIR is not greater than NEXT₋₋ MAX at step 222, or if a validcorrection cannot be made at step 224, then step 226 is skipped.

At step 228 the COUNTER is incremented and control branches to thebeginning of the loop. If at step 206 the COUNTER value is 72 through74, then the parity for the current EDC code word has been completelygenerated. Therefore, the parity for the next EDC code word is updatedat step 230 by adding the current NRZ bit to NEXT₋₋ PARITY and skippingthe parity update for the current EDC code word at step 208.

If the COUNTER value is 75 at step 206, then the error pattern detector146 has completed processing the current EDC code word. Therefore, atstep 232 the parity syndrome for the current EDC code word CUR₋₋ PARITYis evaluated. If non-zero, indicating that a detection error occurred,then at step 234 the error is corrected using the current correctionsequence CUR₋₋ COR stored in register 194 of FIG. 9 and the currentlocation CUR₋₋ LOC stored in register 198. Then at step 236, the systemvariables are re-initialized: the COUNTER is reset to 5; the currentparity CUR₋₋ PARITY is set to NEXT₋₋ PARITY, the parity calculated forthe next EDC code word; the current FIR maximum CUR₋₋ MAX is set toNEXT₋₋ MAX, the maximum FIR output saved for the next EDC code word; andthe parity and correction sequence for the next EDC code word, NEXT₋₋PARITY and NEXT₋₋ COR, are set to zero. Then the flow diagram of FIG. 10is re-executed for the next EDC code word until the end of the sector isreached at step 238.

FIG. 11B shows further details of the circuitry employed to track theparity and maximum FIR error events for the current and next EDC codewords. The detected NRZ sequence 136 output by the EPR4 sequencedetector 134 of FIG. 6 is accumulated for the current and next EDC codewords in registers 242a and 242b, respectively. The parity for thecurrent EDC code word is updated when the COUNTER 240a equals 3 through71, and the parity for the next EDC code word is updated when theCOUNTER 240b equals 72 through 74. When the COUNTER equals 75, theparity for the next EDC code word stored in register 242b is transferredto the parity for the current EDC code word in register 242a.

The SNRZI sequence 154 generated by the remodulator 138 of FIG. 6 isbuffered in FIFO 202, which is the same FIFO shown in FIG. 11A. When theparity for the current EDC code word stored in register 242a indicatesthat a detection error was made by the EPR4 sequence detector 134, theerror corrector 150 uses the maximum error event detected by the errorpattern detector 146 to correct the error in the SNRZI sequence 154.

The two error events E1(n) and E2(n) detected by the two FIR errorfilters 180 of FIG. 9 are compared at comparator 182 and the maximum ofthe absolute value selected as the output of the comparator 182. Themaximum error filter output is compared to the maximum for the currentEDC code word at comparator 244a when the COUNTER 240c equals 3 through74, and to the maximum for the next EDC code word at comparator 244bwhen the COUNTER 240d equals 70 through 74. The maximum error event(location and correction sequence) for the current EDC code word isstored in register 246a, and the maximum error event for the next EDCcode word is stored in register 246b. When the COUNTER equals 75, themaximum error event (location and correction sequence) for the currentEDC code word is used to correct the current EDC code word if thecurrent parity stored in register 242a is non-zero. Then the maximumerror event (correction and location sequence) for the next EDC codeword stored in register 246b is transferred to the current maximum errorevent stored in register 246a. The COUNTER is reset to 5, and theprocedure begins again for the next EDC code word.

A better understanding of how the error corrector 150 of FIG. 6 correctsan error in the detected SNRZI sequence is understood with reference tothe block diagram of FIG. 12. When the error syndrome (parity) generatedby the syndrome generator 148 of FIG. 6 indicates a detection erroroccurred in the current EDC code word, the error corrector 150 receivesfrom the PR4/EPR4 error pattern detector 146 of FIG. 9 the location ofthe maximum error event over line 250 and the corresponding correctedSNRZI sequence over line 252. The corrected SNRZI sequence is stored inregister 254 and applied to a first input of multiplexers 256a-256d. Thedetected SNRZI sequence 154 is shifted through a shift register 258,wherein the output of delay elements 260a-260d are applied to a secondinput of multiplexers 256a-256d. The location of the maximum errorevent, LOCATION 250, controls the operation of the multiplexers256a-256d in order to replace the erroneous bits in the detected SNRZIsequence with the corrected SNRZI sequence at the appropriate time. Theoutput lines of register 254 labeled S_(n), S_(n-1), S_(n-2) and S_(n-3)correspond to the corrected SNRZI sequences shown in Table 4 and Table 5discussed above.

The objects of the invention have been fully realized through theembodiments disclosed herein. Those skilled in the art will appreciatethat the various aspects of the invention can be achieved throughdifferent embodiments without departing from the essential function.Using an EDC error syndrome to guide a remod/demod sequence detector isa broad concept applicable to the prior art as well as to the particularEPR4 remod/demod sequence detector disclosed in FIG. 6. Furthermore,those skilled in the art will appreciate that EDC codes other thanparity could be employed to detect when the trellis detector has made adetection error in the preliminary binary sequence. Still further, theEPR4 remod/demod sequence detector of the present invention employs atleast two significant ideas: the first is to equalize the channelsamples into a PR4 response so that a simple slicer can generateestimated sample values for use by timing recovery, gain control, andthe adaptive discrete-time equalizer; and the second is to search forerror events in at least two different domains, such as in the PR4 andEPR4 domains. However, the particular embodiments disclosed areillustrative and not meant to limit the scope of the invention asappropriately construed from the following claims.

I claim:
 1. A sampled amplitude read channel for reading data recordedon a disk storage medium by detecting data from a sequence ofdiscrete-time sample values generated by sampling pulses in an analogread signal from a read head positioned over the disk storage medium,comprising:(a) a sampling device for sampling the analog read signal togenerate the discrete-time sample values; (b) a discrete-time equalizerfor equalizing the sample values according to a desired partial responseto generate equalized sample values; and (c) a remod/demod sequencedetector for detecting the data from the equalized sample values,comprising:(i) a demodulator, responsive to the equalized sample values,for detecting a binary sequence having one or more bit errors; (ii) asyndrome generator, responsive to the detected binary sequence, forgenerating an error syndrome corresponding to the one or more biterrors; (iii) a remodulator for remodulating the binary sequence into asequence of estimated sample values; (iv) an error value generator,responsive to the equalized sample values and the estimated samplevalues, for generating a sequence of sample error values; (v) an errorpattern detector, responsive to the sequence of sample error values, fordetecting a magnitude and location of the bit errors in the binarysequence; and (vi) an error corrector, responsive to the magnitude andlocation of the bit errors and to the error syndrome, for correcting thebinary sequence.
 2. The sampled amplitude read channel as recited inclaim 1, further comprising a redundancy generator for generating atleast one redundancy bit appended to the data before recording the datato the disk storage medium, wherein the syndrome generator uses theredundancy bit during a read operation to generate the error syndrome.3. The sampled amplitude read channel as recited in claim 2, wherein theredundancy bit represents a parity over a predetermined number of databits.
 4. The sampled amplitude read channel as recited in claim 1,wherein the demodulator outputs a sign and magnitude of the binarysequence.
 5. The sampled amplitude read channel as recited in claim 1,wherein the remodulator comprises a NRZI converter for converting thebinary sequence into a NRZI sequence.
 6. The sampled amplitude readchannel as recited in claim 1, wherein the remodulator comprises anon-linearity compensator which compensates for non-linear distortionsin the read signal.
 7. The sampled amplitude read channel as recited inclaim 6, wherein the non-linearity compensator compensates for thenon-linear reduction in amplitude of a primary pulse caused by secondarypulses located near the primary pulse.
 8. The sampled amplitude readchannel as recited in claim 1, wherein the error pattern detectorcomprises a discrete-time filter matched to a predetermined error event.9. The sampled amplitude read channel as recited in claim 1, furthercomprising a means for converting the sequence of sample error valuesfrom a first partial response domain to a second partial responsedomain, wherein the error pattern detector detects the bit errors in thesecond partial response domain.
 10. The sampled amplitude read channelas recited in claim 1, wherein the demodulator comprises an EPR4sequence detector.
 11. The sampled amplitude read channel as recited inclaim 1, further comprising an error detection validator for checkingthe validity of a detected error event.
 12. The sampled amplitude readchannel as recited in claim 1, wherein the error corrector corrects anerror in the detected binary sequence when the error syndrome indicatesthat the detected binary sequence contains an error.
 13. The sampledamplitude read channel as recited in claim 1, wherein the errorcorrector corrects an error in the detected binary sequence using themagnitude and location of the error generated by the error patterndetector when the error syndrome indicates that the binary sequencecontains an error.
 14. The sampled amplitude read channel as recited inclaim 13, further comprising a data buffer for buffering a predeterminednumber of bits in the detected binary sequence, wherein:(a) the errorpattern detector detects a plurality of potential error events withinthe binary sequence buffered in the data buffer; and (b) the errorpattern detector evaluates the error events to determine the error eventmost likely to have actually caused an error in the detected binarysequence.
 15. The sampled amplitude read channel as recited in claim 1,further comprising:(a) an input connected to receive the data to bewritten to the disk storage medium; and (b) a data encoder for encodingthe data according to an error detection code before the data is writtento the disk storage medium, wherein the syndrome generator generates theerror syndrome according to the error detection code.
 16. The sampledamplitude read channel as recited in claim 1, further comprising:(a) aninput connected to receive the data to be written to the disk storagemedium; (b) a data encoder for encoding n bits of the data into m-bitcode words according to a code constraint; and (c) a redundancygenerator, responsive to at least two of the code words, for generatingat least one redundancy bit appended to the code words before recordingthe code words to the disk storage medium, wherein the syndromegenerator uses the redundancy bit during a read operation to generatethe error syndrome.
 17. The sampled amplitude read channel as recited inclaim 16, wherein the code constraint is a run-length-limited (RLL) codeconstraint.
 18. A sampled amplitude read channel for reading datarecorded on a disk storage medium by detecting data from a sequence ofdiscrete-time sample values generated by sampling pulses in an analogread signal from a read head positioned over the disk storage medium,comprising:(a) a sampling device for sampling the analog read signal togenerate the discrete-time sample values; (b) a timing recovery circuit,responsive to the discrete-time sample values, for generatingsynchronous sample values substantially synchronized to a baud rate ofthe recorded data; and (c) a remod/demod sequence detector for detectingthe data from the synchronous sample values, comprising:(i) ademodulator, responsive to the synchronous sample values, for detectinga binary sequence having one or more bit errors; (ii) a syndromegenerator, responsive to the detected binary sequence, for generating anerror syndrome corresponding to the one or more bit errors; (iii) aremodulator for remodulating the binary sequence into a sequence ofestimated sample values; (iv) an error value generator, responsive tothe synchronous sample values and the estimated sample values, forgenerating a sequence of sample error values; (v) an error patterndetector, responsive to the sequence of sample error values, fordetecting a magnitude and location of the bit errors in the binarysequence; and (vi) an error corrector, responsive to the magnitude andlocation of the bit errors and to the error syndrome, for correcting thebinary sequence.
 19. The sampled amplitude read channel as recited inclaim 18, further comprising a redundancy generator for generating atleast one redundancy bit appended to the data before recording the datato the disk storage medium, wherein the syndrome generator uses theredundancy bit during a read operation to generate the error syndrome.20. The sampled amplitude read channel as recited in claim 19, whereinthe redundancy bit represents a parity over a predetermined number ofdata bits.
 21. The sampled amplitude read channel as recited in claim18, wherein the remodulator comprises a non-linearity compensator whichcompensates for non-linear distortions in the read signal.
 22. Thesampled amplitude read channel as recited in claim 18, wherein the errorcorrector corrects an error in the detected binary sequence when theerror syndrome indicates that the binary sequence contains an error. 23.The sampled amplitude read channel as recited in claim 18, wherein theerror corrector corrects an error in the detected binary sequence usingthe magnitude and location of the error generated by the error patterndetector when the error syndrome indicates that the binary sequencecontains an error.
 24. The sampled amplitude read channel as recited inclaim 23, further comprising a data buffer for buffering a predeterminednumber of bits in the detected binary sequence, wherein:(a) the errorpattern detector detects a plurality of potential error events withinthe binary sequence buffered in the data buffer; and (b) the errorpattern detector evaluates the error events to determine the error eventmost likely to have actually caused an error in the detected binarysequence.
 25. The sampled amplitude read channel as recited in claim 18,further comprising:(a) an input connected to receive the data to bewritten to the disk storage medium; (b) an encoder for encoding n bitsof the data into m-bit code words according to a code constraint; and(c) a redundancy generator, responsive to at least two of the codewords, for generating at least one redundancy bit appended to the codewords before recording the code words to the disk storage medium,wherein the syndrome generator uses the redundancy bit during a readoperation to generate the error syndrome.
 26. A sampled amplitude readchannel for reading recorded data from a disk storage medium bydetecting the recorded data from a sequence of discrete-time samplevalues generated by sampling pulses in an analog read signal from a readhead positioned over the disk storage medium, comprising:(a) a samplingdevice for sampling the analog read signal to generate the discrete-timesample values; (b) a discrete-time sequence detector for detecting apreliminary sequence from the discrete-time sample values; (c) asyndrome generator, responsive to the preliminary sequence, forgenerating an error syndrome; (d) a remodulator for remodulating thepreliminary sequence into a sequence of estimated sample values; (e) anerror pattern detector, responsive to the discrete-time sample valuesand the estimated sample values, for detecting an error event in thepreliminary sequence; (f) an error detection validator for checking avalidity of the detected error event with respect to the estimatedsample values; and (g) an error corrector, responsive to the errorpattern detector and the syndrome generator, for correcting errors inthe preliminary sequence to thereby generate a corrected sequence. 27.The sampled amplitude read channel as recited in claim 26, furthercomprising:a sample error generator, responsive to the discrete-timesample values and the estimated sample values, for generating a sampleerror sequence.
 28. The sampled amplitude read channel as recited inclaim 27, wherein the error pattern detector detects the error eventusing the sample error sequence.
 29. The sampled amplitude read channelas recited in claim 26, wherein the error pattern detector comprises aplurality of FIR filters matched to minimum distance error events of thediscrete-time sequence detector.
 30. The sampled amplitude read channelas recited in claim 26, further comprising:(a) an input connected toreceive user data from a host system; (b) an encoder for encoding theuser data according to a code constraint to generate encoded data; and(c) a redundancy generator, responsive to the encoded data, forgenerating at least one redundancy bit appended to the encoded databefore recording the encoded data to the disk storage medium, whereinthe syndrome generator uses the redundancy bit during a read operationto generate the error syndrome.
 31. The sampled amplitude read channelas recited in claim 26, further comprising a run-length limited (RLL)decoder for decoding the detected binary sequence into a decoded binarysequence according to an RLL (d,k) constraint.
 32. The sampled amplituderead channel as recited in claim 26, wherein:(a) the error patterndetector generates a correction sequence and location for an error inthe binary sequence; and (b) the error corrector uses the correctionsequence and location of the errors to correct the binary sequence. 33.The sampled amplitude read channel as recited in claim 26, wherein:(a)the recorded data comprises redundancy data; (b) the discrete-timesequence detector operates according to a state transition diagramresponsive to a first part of the redundancy data; and (c) the syndromegenerator generates the error syndrome responsive to a second part ofthe redundancy data.
 34. A method for reading data recorded on a diskstorage medium by detecting data from a sequence of discrete-time samplevalues generated by sampling pulses in an analog read signal from a readhead positioned over the disk storage medium, comprising the stepsof:(a) sampling the analog read signal to generate the discrete-timesample values; (b) detecting a binary sequence from the equalized samplevalues; (c) remodulating the binary sequence into a sequence ofestimated sample values; (d) generating a sample error sequence from thediscrete-time sample values and the estimated sample values; (e)detecting an error event in the sample error sequence; (f) generating anerror syndrome from the binary sequence; and (g) correcting the biterrors in the binary sequence using the error event detected in step (e)and the error syndrome generated in step (f).
 35. A sampled amplituderead channel for reading recorded data from a disk storage medium bydetecting the recorded data from a sequence of discrete-time samplevalues generated by sampling pulses in an analog read signal from a readhead positioned over the disk storage medium, comprising:(a) a samplingdevice for sampling the analog read signal to generate the discrete-timesample values; and (b) a discrete-time sequence detector for detecting apreliminary sequence from the discrete-time sample values; (c) asyndrome generator for generating an error syndrome in response to thepreliminary sequence; (d) a remodulator for remodulating the preliminarysequence into a sequence of estimated sample values; (e) an errorpattern detector, responsive to the estimated sample values, fordetecting an error event in the preliminary sequence; and (f) an errorcorrector, responsive to the error syndrome and the error patterndetector, for correcting errors in the preliminary sequence.
 36. Thesampled amplitude read channel as recited in claim 35, furthercomprising:a sample error generator, responsive to the discrete-timesample values and the estimated sample values, for generating a sampleerror sequence.
 37. The sampled amplitude read channel as recited inclaim 36, wherein the error pattern detector uses the sample errorsequence to detect the error event.
 38. The sampled amplitude readchannel as recited in claim 37, wherein the error pattern detectorcomprises a plurality of FIR filters matched to minimum distance errorevents of the discrete-time sequence detector.
 39. The sampled amplituderead channel as recited in claim 35, wherein the error pattern detectorcomprises a validator for checking a validity of the detected errorevent with respect to the estimated sample values.
 40. The sampledamplitude read channel as recited in claim 35, wherein the errorsyndrome is computed as parity over a predetermined number of bits inthe binary sequence.